library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity TB_quattro is
end TB_quattro;

architecture TEST of TB_quattro is
component quattro is
generic (		NUMBIT	: integer := 4;
			ROMSIZE	: integer := 8;
			RAMSIZE	: integer := 4);
port(	clock	 			: in  std_logic;
		reset	 			: in  std_logic;					
		final_result			: out std_logic_vector (NUMBIT-1 downto 0)
);
end component;

signal result : std_logic_vector(3 downto 0);
signal CLK : std_logic:= '0';
signal RST : std_logic ;
begin

CPU_UUT: quattro port
map(	clock	  => CLK,
		reset	  => RST,
		final_result => result
);

CLK_P: process (CLK)
	begin
		CLK <= not (CLK) after 15 ns;
	end process;

RST		<=	'1', '0' after 13 ns;

end TEST;
